On-board fault-tolerant SAR processor for spaceborne imaging radar systems

A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.

[1]  R. J. Beynon,et al.  Computers , 1985, Comput. Appl. Biosci..

[2]  M. E. Davis,et al.  A joint space-borne radar technology demonstration mission for NASA and the Air Force , 2003, 2003 IEEE Aerospace Conference Proceedings (Cat. No.03TH8652).

[3]  Richard W. Linderman,et al.  A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing , 1998, IEEE Trans. Computers.