A Low-power 7-b 33-Msamples/s Switched-current Pipelined ADC for Motor Control

This paper presents the design and implementation of a low-power three-stage switched-current pipelined analog-to-digital converter. Its sub-circuit includes current-mode S/H, current-mode subtractor, current-mode DAC, I/V converter, voltage-mode folding ADC, current-mode reference, error correction circuit, and so on. With the view to implement a high speed and low power consumption pipelined ADC, both the switched-current technique and the I/V converter are considered. Besides, an error correction circuit is also considered, even though it wastes one bit at the inter-stage. The simulated results show that there are some advantages within the proposed pipelined ADC: high sampling frequency (up to 33 MHz), low power consumption (about 276 mW), and small chip area (1 mm2). Furthermore, the maximum value of the signal to noise and distortion ratio (SNDR) is greater than 42dB (about 7 bits) with a 3.3V power supply

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