FPGA implementation of an excitatory and inhibitory connectionist model for motion perception

Based on neurophysiological studies of the visual cortex, the design and FPGA implementation of a bio-inspired hardware architecture for visual perception of motion is presented. The architecture is based on a neural model that mimics the way in which the visual stimuli is processed in the visual cortex pathways by means of spatio-temporal filtering and excitatory-inhibitory neural processing. This paper mostly develops the time-multiplexed and connection-parallelized implementation of the densely interconnected module that performs excitatory and inhibitory computation loops. The architecture modules have been modeled in VHDL and independently synthesized for an FPGA device. The obtained results show the plausibility of efficient implementation of bio-inspired models through embeddable specialized hardware architectures restricted to real-time constraints.

[1]  Brendan McCane,et al.  On Benchmarking Optical Flow , 2001, Comput. Vis. Image Underst..

[2]  André DeHon,et al.  The Density Advantage of Configurable Computing , 2000, Computer.

[3]  Kwabena Boahen,et al.  Competitively coupled orientation selective cellular neural networks , 2002 .

[4]  Eero P. Simoncelli,et al.  A model of neuronal responses in visual area MT , 1998, Vision Research.

[5]  César Torres-Huitzil,et al.  Real-time image processing with a compact FPGA-based systolic architecture , 2004, Real Time Imaging.

[6]  Dan Hammerstrom,et al.  Digital VLSI for neural networks , 1998 .

[7]  B. Girau,et al.  Digital implementation of a bio-inspired neural model for motion estimation , 2005, Proceedings. 2005 IEEE International Joint Conference on Neural Networks, 2005..

[8]  Bernard Girau,et al.  FPNA: Interaction Between FPGA and Neural Computation , 2000, Int. J. Neural Syst..

[9]  Alan A. Stocker,et al.  Analog VLSI focal-plane array with dynamic connections for the estimation of piecewise-smooth optical flow , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Bertram E. Shi,et al.  An ON-OFF orientation selective address event representation image transceiver chip , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Bertil Svensson,et al.  Using and Designing Massively Parallel Computers for Artificial Neural Neural Networks , 1992, J. Parallel Distributed Comput..

[12]  Bernard Girau,et al.  A CONNECTIONIST APPROACH FOR VISUAL PERCEPTION OF MOTION , 2004 .