A 40Gb/s TX and RX chip set in 65nm CMOS

Next generation optical and electrical communications such as chip-to-chip serial links or 100GbE require very-high-speed transceivers. At tens of Gb/s, both transmitters and receivers suffer from inadequate bandwidth and high power consumption. One major difficulty arises from the performance degradation of FIR-based FFEs as the FF's CK-Q delay becomes significant to one bit period. Using passive components as delay elements [1][2] can relax this issue to some extent, but the untunable delay is quite vulnerable to PVT variations. Traditional DFEs also suffer from speed limitation in its feedback loop, and parallelization schemes usually introduce complex circuits and high power consumption. This paper presents a full-rate 40Gb/s transceiver prototype significantly alleviating the above issues.