24 Bit seismic processor for analyzing extra large dynamic range signals for early warnings

Modified design is presented of existing 24 bit seismic data recorder comprising PC -architecture using PCI bus, ISA bus, and PC 104 bus in a single module to develop a flexible measurement set up. Paper elaborates use of building blocks [Disk on chip (DoC), GPS based timing unit, signal-processing module, and efficient software packages] worked out in visual C++ to develop compact sized instrument for quick decision-making with minimum error detection of true events. Paper describes Ethernet connectivity use for data downloading in a laptop without interruption of event data acquisition. Software packages for conversion of recorded data into SUDS and SEISAN formats have been realized and incorporated.