Low-power small-area /spl plusmn/7.28 ps jitter 1 GHz DLL-based clock generator

A 1 GHz DLL-based clock generator in 0.35 /spl mu/m CMOS occupies 0.08 mm/sup 2/. It has fast locking time and no jitter-accumulation problem. A phase detector with reset circuitry and a frequency multiplier overcome the limited locking range and frequency multiplication problem of conventional DLL-based systems. Measured peak-to-peak jitter is /spl plusmn/7.28 ps.

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