New 3-D Chip Stacking Architectures by Wire-On-Bump and Bump-On-Flex
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R.R. Tummala | Baik-Woo Lee | Jui-Yun Tsai | Hotae Jin | C.K. Yoon | R. Tummala | J. Tsai | B. Lee | H. Jin | C. Yoon
[1] V. Kripesh,et al. Three-dimensional system-in-package using stacked silicon platform technology , 2005, IEEE Transactions on Advanced Packaging.
[2] M. Karnezos,et al. 3D packaging: where all technologies come together , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).
[3] Kuo-Ning Chiang,et al. Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging , 2002 .
[4] J. H. Lau,et al. Solder joint reliability of a low cost chip size package—NuCSP , 1998 .
[5] J. Pang,et al. Lead-free 95.5Sn-3.8Ag-0.7Cu solder joint reliability analysis for micro-BGA assembly , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).
[6] S. Holmes,et al. Processing thick multilevel polyimide films for 3-D stacked memory , 1999, ECTC 1999.
[7] Fei Su,et al. Prediction and verification of process induced warpage of electronic packages , 2003, Microelectron. Reliab..
[8] Yi-Ming Jen,et al. Impact of the number of chips on the reliability of the solder balls for wire-bonded stacked-chip ball grid array packages , 2006, Microelectron. Reliab..
[9] R. M. Lea,et al. A 3-D stacked chip packaging solution for miniaturized massively parallel processing , 1999 .
[10] Vivek Arora,et al. Numerical and experimental analysis of large passivation opening for solder joint reliability improvement of micro SMD packages , 2004, Microelectron. Reliab..
[11] Guo-Quan Lu,et al. Flip-chip on flex integrated power electronics modules for high-density power integration , 2003 .
[12] Keith A. Jenkins,et al. Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection , 2005, IBM J. Res. Dev..
[13] K. Matsui,et al. Optimization for chip stack in 3-D packaging , 2005, IEEE Transactions on Advanced Packaging.