Novel analysis model for investigation of contact force and scrub length for design of probe card

Abstract Fabrication defects in IC chips are generally identified using a multi-layer needle probe card. To prolong the life of the card, the needles in each layer should experience a similar contact force and should produce a scrub mark of minimal length. To facilitate the probe card design process, this paper proposes an analytical model for evaluating the contact force and scrub mark length of a single-needle probe as a function of the overdrive distance. The model is based on Castigliano’s displacement theorem and takes account of both the material and the geometric properties of the needle. The validity of the analytical model is confirmed by performing a series of finite-element simulations at overdrive distances ranging from 30 to 70 μm. In addition, experimental probe card tests are performed using a tungsten needle probe and an aluminum pad. A good agreement is found between the experimental and analytical results for overdrive distances in the range 50 ± 10 μm. Overall, the results presented in this study confirm that the proposed analytical model provides an accurate and convenient means of determining the optimal needle probe design given maximum permissible values of the contact force and scrub mark length, respectively.

[1]  Robert L. Franch,et al.  Advances In Membrane Probe Technology , 1992, Proceedings International Test Conference 1992.

[2]  De-Shin Liu,et al.  Experimental aided performance evaluation methods for wafer probe test , 2006 .

[3]  W. H. Huang,et al.  Measurement and analysis of contact resistance in wafer probe testing , 2007, Microelectron. Reliab..

[4]  Farid Matta,et al.  Membrane probe card technology (the future for higher performance wafer test) , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[5]  M. J. Varnau Impact of wafer probe damage on flip chip yields and reliability , 1996, Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium.

[6]  G. Hotchkiss,et al.  Effects of probe damage on wire bond integrity , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[7]  Jerry J. Broz,et al.  Probe contact resistance variations during elevated temperature wafer test , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[8]  Frederick L. Taber An introduction to area array probing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  Wolfgang Sauter,et al.  Problems with wirebonding on probe marks and possible solutions , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[10]  Chung-Yi Lin,et al.  High density vertical probe card fabrication with low cost and high precision characteristics by using MEMS process , 2005, 2005 7th Electronic Packaging Technology Conference.

[11]  Dar-Yuan Chang,et al.  Geometric parameter design of a cantilever probing needle used in epoxy ring probe card , 2009 .

[12]  D.S. Liu,et al.  An Experimental and Numerical Investigation Into Multilayer Probe Card Layout Design , 2006, IEEE Transactions on Electronics Packaging Manufacturing.

[13]  De-Shin Liu,et al.  An Investigation of Wafer Probe Needles Mechanical Properties and Contact Resistance Changing Under Multiprobing Process , 2008, IEEE Transactions on Components and Packaging Technologies.

[14]  D. S. Liu,et al.  Experimental method and FE simulation model for evaluation of wafer probing parameters , 2006, Microelectron. J..

[15]  C. Beddingfield,et al.  Reliability evaluation of probe-before-bump technology , 1999, Twenty Fourth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.99CH36330).

[16]  Y. Deguchi,et al.  Highly reliable probe card for wafer testing , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[17]  De-Shin Liu,et al.  Application of a Genetic Algorithm to the Design Optimization of a Multilayer Probe Card for Wafer-Level Testing , 2009 .