A crystalline oxide semiconductor (OS) FPGA capable of subthreshold operation is developed. To achieve subthreshold operation, the OS FPGA employs overdriving of a programmable routing switch and a programmable power switch for power gating by using OS FFT as an ideal floating gate with excellent charge retention. In a prototype chip fabricated with a 0.8-m OS/0.18-m CMOS hybrid process, while maintaining features realizing low power consumption proposed in our previous studies [1, 2], the following are shown: a configured combinational circuit operates at a minimum operating voltage (Vmin) of 180 mV, a configured sequential circuit operates at Vmin of 190 mV with 12.5 kHz, and the minimum power-delay product scores 3.40 pJ/operation at 330 mV.