An adaptive supply-voltage scheme for low power self-timed CMOS digital design

This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement. This adaptive supply-voltage scheme employs the handshake signals directly to detect the speed of data path without using FIFO buffer. This leads to a very simple logic control whose power loss is negligible. Cadence SPICE simulation shows the effectiveness of this scheme for low power applications based on 0.18 /spl mu/m CMOS process.

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