The key of 1000 Base-T Ethernet frequency synthesizer is a charge-pump phase locked loop. The PLL is designed with a new high speed phase and frequency detector (TSPC),a low-power noise-suppressed charge pump and typical symmetrical-load differential delay cells PLL,which makes the circuit work stably. Meanwhile,the circuit has small clock jitter under different temperatures and process conditions. System stability verification and spice simulation show the 125 MHz output clock is about 70 ps (75 ℃ @ TT).For three different process conditions the circuit can also meet the specification perfectly with 0.1 V_(P-P) noise supply.(In 1000 Base-T, Δt=8 ns/16=500 ps.According to the CDR algorithm,more strict requirement of jitter_(peak-peak) is about (2%-3%)×baud=160-240 ps). The power supply is (1.8 V) and 0.18 μs standard CMOS technology is adopted.