Efficient combination of trace and scan signals for post silicon validation and debug

Post-silicon validation is as an important aspect of any integrated circuit design methodology. The primary objective is to capture the bugs that have escaped the pre-silicon validation phase. A major challenge in post-silicon debug is the limited observability of internal signals in the circuit. Recent technological advances, such as embedded logic analysis, allow to store some signal states in a trace buffer. A promising direction to improve observability is to combine a small set of signals traced every cycle with a large set of scan signals stored across several cycles. The limited size of the trace buffer constrains the number of trace and scan signals that can be stored. In this paper, we propose an efficient algorithm to select a profitable combination of trace and scan signals to maximize the overall signal restoration performance. Our experimental results using ISCAS'89 benchmarks demonstrate that our approach can improve the signal restoration by 17% compared to the existing techniques.

[1]  Bart Vermeulen,et al.  Silicon debug: scan chains alone are not enough , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[2]  L. Whetsel,et al.  An analysis of power reduction techniques in scan testing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[3]  Prabhat Mishra,et al.  Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Ismet Bayraktaroglu,et al.  Microprocessor silicon debug based on failure propagation tracing , 2005, IEEE International Conference on Test, 2005..

[5]  Doug Josephson,et al.  The crazy mixed up world of silicon debug [IC validation] , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[6]  Nicola Nicolici,et al.  Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Xinli Gu,et al.  Re-using DFT logic for functional and silicon debugging test , 2002, Proceedings. International Test Conference.

[8]  Alan J. Hu,et al.  BackSpace: Formal Analysis for Post-Silicon Debug , 2008, 2008 Formal Methods in Computer-Aided Design.

[9]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  Andreas G. Veneris,et al.  Automated data analysis solutions to silicon debug , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Valeria Bertacco,et al.  Dacota: Post-silicon validation of the memory subsystem in multi-core designs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[12]  Michael S. Hsiao,et al.  Using Non-trivial Logic Implications for Trace Buffer-Based Silicon Debug , 2009, 2009 Asian Test Symposium.

[13]  Ozgur Sinanoglu,et al.  Revival of partial scan: Test cube analysis driven conversion of flip-flops , 2011, 29th VLSI Test Symposium.

[14]  Priyadarsan Patra.  On the cusp of a validation wall , 2007, IEEE Design & Test of Computers.

[15]  Jacob A. Abraham,et al.  Delay fault testing and silicon debug using scan chains , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[16]  Nicola Nicolici,et al.  Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging , 2010, 2010 15th IEEE European Test Symposium.

[17]  Romain Desplats,et al.  Fault localization using time resolved photon emission and stil waveforms , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[18]  Prabhat Mishra,et al.  Efficient trace data compression using statically selected dictionary , 2011, 29th VLSI Test Symposium.

[19]  Prabhat Mishra,et al.  Efficient Trace Signal Selection for Post Silicon Validation and Debug , 2011, 2011 24th Internatioal Conference on VLSI Design.

[20]  Xiaowei Li,et al.  A New Post-Silicon Debug Approach Based on Suspect Window , 2009, 2009 27th IEEE VLSI Test Symposium.

[21]  Qiang Xu,et al.  Trace signal selection for visibility enhancement in post-silicon validation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.