An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi- $\mathrm{V}_{\rm DD}$ CMOS/SIMOX Techniques

Many of the current wireline networks are digitalized. In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and application data are transferred with a synchronous transfer module (STM). This paper presents an STM-16 frame termination VLSI fabricated with a 0.3-μm quintuple-metal CMOS/SIMOX process. To reduce power consumption, we employ a multiVDD architecture using 2- and 1-V power supplies. Also, fully depleted silicon on insulator (FD-SOI) devices are used to obtain a higher operating speed and to reduce dynamic power dissipation. To install another powerline in every standard cell without increasing the cell size, a stacked multiple powerlines scheme is proposed. In addition, some dedicated standard cells are developed to convert the logical high level without degrading the signal integrity. With regards to hard macros, 2-V MUX/DEMUX macros achieve a high operating speed of 2.5 Gb/s, while a dual-port SRAM macro can operate at a low supply voltage of 1 V. Moreover, 2-V 50-Ω-terminated input/output buffers using a new direct-drive amplifier operate without dedicated power supplies. With our STM-16 frame termination VLSI, the power consumption during the standby is 34 mW, and that for 2.5-Gb/s operation is 1.2 W at 25 °C.

[1]  Y. Ohji,et al.  Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application , 2003, IEEE International Electron Devices Meeting 2003.

[2]  Jerry G. Fossum,et al.  Dynamic floating-body instabilities in partially depleted SOI CMOS circuits , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[3]  S. Narasimha,et al.  22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL , 2012, 2012 International Electron Devices Meeting.

[4]  Y. Ohtomo,et al.  A low-power multi-gigabit CMOS/SIMOX LSI design using two power supply voltages , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[5]  Katsutoshi Izumi,et al.  C.M.O.S. devices fabricated on buried SiO2 layers formed by oxygen implantation into silicon , 1978 .

[6]  Hiroshi Nakamura,et al.  Geyser-2: The second prototype CPU with fine-grained run-time power gating , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[7]  Yuichi Kado,et al.  Suppression of parasitic bipolar action in ultra-thin-film fully-depleted CMOS/SIMOX devices by Ar-ion implantation into source/drain regions , 1998 .

[8]  Yasuhiko Sasaki,et al.  Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.

[9]  H. Inokawa,et al.  Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture , 1999 .

[10]  B. Gunning,et al.  A CMOS low-voltage-swing transmission-line transceiver , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  Stanley E. Schuster,et al.  Fast CMOS ECL receivers with 100-mV worst-case sensitivity , 1988 .

[12]  Luca Benini,et al.  Transformation and synthesis of FSMs for low-power gated-clock implementation , 1995, ISLPED '95.

[13]  L. Wagner,et al.  Transient pass-transistor leakage current in SOI MOSFET's , 1997, IEEE Electron Device Letters.

[14]  Satoshi Shigematsu,et al.  A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application , 1996, IEEE J. Solid State Circuits.

[15]  Takashi Ishikawa,et al.  Automated low-power technique exploiting multiple supply voltages applied to a media processor , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[16]  S. Maegawa,et al.  Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[17]  Chenming Hu,et al.  A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[18]  C. Tretz,et al.  Hysteresis in floating-body PD/SOI CMOS circuits , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[19]  A. Wei,et al.  Minimizing floating-body-induced threshold voltage variation in partially depleted SOI CMOS , 1996, IEEE Electron Device Letters.