A CMOS Variable GainAmplifier withDC Offset Calibration Loop forWireless Communications

A 64dB gainrangeVGA withDC offset Onlywhenthesignal islarge enough that thenoise figure calibration loopisproposed inthiswork.ThisVGA oftheVGA wouldnotbecritical totheperformance ofthe adopts thedegeneration typeamplifier tovaryvoltagereceiver, thegainofthefirst stage ischanged toalower gainandusesthesuper-source-follower input stage to value. Moreover, forverylarge signal, theattenuation in enhancethelinearity. A digital-based DC offsetthefirst stage willenhance thelinearity oftheVGA and calibration loopisalsodesigned tosolve theDC offset increase thetotal IP3. problem. Anexperimental chipisfabricated in0.18im process. With2dBstep, thegainerror isless than0.8