Performance improvement using on-board wires for on-chip interconnects

Utilizing a stochastic global-net length distribution for a projected giga-scale integration (GSI) chip in year 2011, the number of total off-chip layers and pads required for a specified decrease of the maximum on-chip interconnect length are calculated. For example, by adding four off-chip layers to the on-chip interconnects of the projected microprocessor, the global clock frequency can be increased from 3 GHz to 4 GHz, which is the maximum possible value limited by the time of flight delay.