An FPGA-Based Implementation of Fixed-Point Standard-LMS Algorithm with Low Resource Utilization and Fast Convergence

An FPGA-based fixed-point standard-LMS algorithm core is proposed for adaptive signal processing (ASP) realization in real time. The LMS core is designed in VHDL93 language as basis of FIR adaptive filter. FIR adaptive filters are mostly used because of their low computation costs and linear phase. The proposed model uses 12-bit word-length for input data from analog to digital converter (ADC) chip while internal computations are based on 17-bit word-length because of considering guard bits to prevent overflow. The designed core is FPGA- brand-independent so that it can be implemented on any brand to create a system-on- programmable-chip (SoPC). In this paper, XILINX SPARTAN3E and VIRTEX4 FPGA series are used as implementation platform. Rounding errors were inevitable due to limited word-length and can be decreased by adjusting the dynamic range of input signal amplitude. A comparison is made between DSP, Hardware/Software co-design and pure-hardware implementations. Obtained results show improvements in area-resource utilization, convergence speed and performance in the designed pure-hardware LMS core. Although using a pure-hardware implementation results in high performance, it is much more complex than other structures. Copyright © 2010 Praise Worthy Prize S.r.l. - All rights reserved.

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