Combinational equivalence checking through function transformation
暂无分享,去创建一个
[1] Thomas R. Shiple,et al. Building Circuits from Relations , 2000, CAV.
[2] A. Kuehlmann,et al. Equivalence Checking Using Cuts And Heaps , 1997, Proceedings of the 34th Design Automation Conference.
[3] Carl-Johan H. Seger,et al. CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination , 2001, CAV.
[4] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[5] In-Ho Moon,et al. Simplifying Circuits for Formal Verification Using Parametric Representation , 2002, FMCAD.
[6] D. Brand. Verification of large synthesized designs , 1993, ICCAD 1993.
[7] Eduard Cerny,et al. Tautology checking using cross-controllability and cross-observability relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[8] D. Brand. Verification of large synthesized designs , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[9] Andreas Kuehlmann,et al. Equivalence checking combining a structural SAT-solver, BDDs, and simulation , 2000, Proceedings 2000 International Conference on Computer Design.
[10] Robert K. Brayton,et al. Using SAT for combinational equivalence checking , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[11] F. Somenzi,et al. To split or to conjoin: the question in image computation , 2000, Proceedings 37th Design Automation Conference.
[12] Carl-Johan H. Seger,et al. Parametric Representations of Boolean Constraints. , 1999, DAC 1999.
[13] In-Ho Moon,et al. Border-Block Triangular Form and Conjunction Schedule in Image Computation , 2000, FMCAD.
[14] Carl-Johan H. Seger,et al. Formal verification using parametric representations of Boolean constraints , 1999, DAC '99.
[15] Andrew B. Kahng,et al. Improved algorithms for hypergraph bipartitioning , 2000, ASP-DAC '00.
[16] Joao Marques-Silva,et al. Combinational equivalence checking using satisfiability and recursive learning , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).