Design Patterns for Graceful Degradation

Graceful degradation describes the smooth change of some distinct system feature to a lower state as a response to an event that prevents the system from exhibiting that feature in its full state. Such system behavior has appeared in a variety of domains from image processing and telecommunications to shared memory multiprocessors and multi-modular memory systems. In each domain, graceful degradation has targeted a different system feature, e.g. image quality, voice quality, computational capacity, memory access throughput, etc. However, irrespectively of the system feature that has been gracefully degraded, the basic concepts behind the mechanisms responsible for this behavior have been similar. This paper presents a design pattern that captures the general idea behind graceful degradation, plus three more patterns that describe how to smoothly reach a lower system state under different circumstances.

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