FPGA based implementation of low latency multichannel satellite modulator with packet loss detection

This paper explains the implementation of a packet based multichannel scalable satellite modulator using efficient, novel Data buffering technique and packet loss management in FPGA. The modulator receives data packets from IP network and sends it to satellite network after processing. The scheme allows for loss-less transfer of data from Best effort IP based packet network to a circuit switched fixed bit rate narrow band continuous satellite modulator using a novel and very low latency scheme. The process is improvised to reduce latency without compromising on probability threshold of packed loss, for the required data transmission rate. The multichannel modulator design is implemented in Xilinx Virtex-6 FPGA. The IP packet processed in another device reaches FPGA via EMIF interface as RAW blocks of data packet of multiple channels. The buffered data is serialized and modulated. The data is processed through [1] INTELSAT V.35 Scrambler, Differential encoder, 1/2 rate convolutional encoder, RRC filtering and BPSK modulator. If packet is not received, then the buffer is cleared and packet-loss count is incremented. This count is used for performance analysis of the design.