A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 μm CMOS

Abstract This paper presents a 10bit 20 kS/s 9.1ENOB SAR ADC employing an energy-efficient and highly-linear capacitor switching strategy in 0.18 μm CMOS process. The SAR ADC with this proposed strategy features better linearity due to the use of a relatively lower assistant reference, the value of which is equivalent to a quarter of the input swing. In addition, the accuracy of the assistant reference has no impact on the ADC performance, since only this assistant reference will be involved with the capacitive DACs during the conversion period. The ADC is powered by the supplies of 0.6 V/0.15 V. The capacitive DACs are supplied by the 0.15 V assistant reference, while the other blocks are powered by the 0.6 V reference. In this case, the ADC consumes 11.7 nW overall, resulting in a figure-of-merit (FOM) of 1.6fJ/conversion-step. At a 20-kS/s output rate, the measured results show the proposed SAR ADC performs a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB, a peak spurious-free-dynamic-range (SFDR) of 66.7 dB. The core area of the designed ADC is and 370 × 310 μm2.

[1]  Soon-Jyh Chang,et al.  10-bit 30-MS/s SAR ADC Using a Switchback Switching Method , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Eric A. M. Klumperink,et al.  A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s , 2010, IEEE Journal of Solid-State Circuits.

[3]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[4]  Ameya Bhide,et al.  A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-$\mu$m CMOS for Medical Implant Devices , 2012, IEEE Journal of Solid-State Circuits.

[5]  Soon-Jyh Chang,et al.  A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process , 2009, 2009 Symposium on VLSI Circuits.

[6]  Jae-Yoon Sim,et al.  A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Jon Guerber,et al.  Merged capacitor switching based SAR ADC with highest switching energy-efficiency , 2010 .

[8]  Yi Xie,et al.  A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  S. Narendra,et al.  Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.

[10]  Atila Alvandpour,et al.  A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Zhangming Zhu,et al.  A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices. , 2015 .