Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application
暂无分享,去创建一个
Qiang Zhao | Xuan Zeng | Changyong Liu | Xiulong Wu | Chunyu Peng | Zhiting Lin | Junning Chen | Jiati Huang | Songsong Xiao | Xuan Zeng | Junning Chen | Xiulong Wu | Chunyu Peng | Zhiting Lin | Qiang Zhao | Changyong Liu | Songsong Xiao | Jiati Huang
[1] Shuming Chen,et al. Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation , 2012, IEEE Transactions on Device and Materials Reliability.
[2] S. Jahinuzzaman,et al. A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability , 2009, IEEE Transactions on Nuclear Science.
[3] J. S. Kauppila,et al. An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology , 2016, IEEE Transactions on Nuclear Science.
[4] K. Stawiasz,et al. Low Energy Proton SEUs in 32-nm SOI SRAMs at Low Vdd , 2017, IEEE Transactions on Nuclear Science.
[5] John D. Cressler,et al. Using TCAD Modeling to Compare Heavy-Ion and Laser-Induced Single Event Transients in SiGe HBTs , 2017, IEEE Transactions on Nuclear Science.
[6] William H. Robinson,et al. Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization , 2015, IEEE Transactions on Nuclear Science.
[7] Ivan R. Linscott,et al. LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.
[8] R. Baumann. Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .
[9] Bahar Asgari,et al. Design of Robust SRAM Cells Against Single-Event Multiple Effects for Nanometer Technologies , 2015, IEEE Transactions on Device and Materials Reliability.
[10] H.-B Wang,et al. An Area Efficient SEU-Tolerant Latch Design , 2014, IEEE Transactions on Nuclear Science.
[11] Lloyd W. Massengill,et al. Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .
[12] E. Ibe,et al. Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.
[13] Shuming Chen,et al. The Separation Measurement of $P$ -Hit and $N$ -Hit Charge Sharing With an “S-Like” Inverter Chains Test Structure , 2017, IEEE Transactions on Nuclear Science.
[14] T. Calin,et al. Upset hardened memory design for submicron CMOS technology , 1996 .
[15] Jing Guo,et al. Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] Bin Liang,et al. Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism , 2012, Microelectron. Reliab..
[17] Mehdi Baradaran Tahoori,et al. Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs) , 2011, 2011 Design, Automation & Test in Europe.
[18] Yong-Bin Kim,et al. Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset , 2012, IEEE Transactions on Device and Materials Reliability.
[19] Ziyang Chen,et al. A radiation harden enhanced Quatro (RHEQ) SRAM cell , 2017, IEICE Electron. Express.
[20] Jie Li,et al. A Highly Reliable Memory Cell Design Combined With Layout-Level Approach to Tolerant Single-Event Upsets , 2016, IEEE Transactions on Device and Materials Reliability.
[21] P. E. Dodd,et al. Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.