Fast System-Level Prototyping of Power-Aware Dynamic Memory Managers for Embedded Systems

The rapid evolution in sub-micron process technology allows presently more complex systems to be implemented in embedded devices. In the near future, portable consumer devices must run multimedia and wireless network applications that require an enormous computational performance (1-40 GOPS) at a low energy consumption (0.1-2 W ). In these multimedia and wireless network applications, the dynamic memory subsystem is currently one of the main sources of power consumption and its inattentive management can severely affect the performance and power consumption of the whole system. Within this context, the construction and system-level power evaluation of custom dynamic memory managers is one of the most important and difficult parts for an efficient mapping of such dynamic applications on low-power and high-speed embedded systems. Moreover, they are subjected to design-time constraints due to market competition. As a result, current design technologies fall behind these requirements and consistent high-level design methodologies able to handle such complexity and enabling a short time-to-market are in great need. In this paper, we present a new system-level approach to model complex custom dynamic memory managers integrating a detailed power profiling method. This approach enables the developer to obtain power consumption estimates, memory usage and memory access values to refine the dynamic memory management of the system in a very early stage of the design flow and to explore the large search space of dynamic memory manager implementations without a time-consuming programming effort.

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