A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface

A fast lock DLL based 800Mb/s to 3.2 Gb/s burst mode memory interface is implemented. The DLL employs a two-step TDC during power up from 0mW to lock within 3 cycles with residual error <; 33 mUI. Following initial lock, the DLL operates closed-loop to compensate for V,T drift consuming 6mW @ 1.6GHz. In addition the DLL filters high frequency input jitter and corrects 20% DCD without additional correction.

[1]  T. Matano,et al.  A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  Chulwoo Kim,et al.  A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces , 2012, IEEE Journal of Solid-State Circuits.