Modeling and analysis of high-speed links

Very low bit error rate (BER) requirements for the operation of a high-speed link system require a very precise analysis of the link performance in order to prevent unrealistic specifications on both IC design and communication algorithm development. This paper presents the analysis of the noise and distortion sources in a high-speed link system, and their impact on the choice and effectiveness of different communication techniques. Phase-locked loop and clock-and-data recovery loop modeling is also described. It is shown that the most dominant noise and distortion sources are colored and bounded, as opposed to standard unbounded Gaussian white noise assumptions, which yield large errors in the estimation of the link performance and comparison of different signaling techniques. With very low BER requirements, shape of probability distribution of noise and distortion sources and their correlations, are much more important than just their total power, which contrasts the standard analysis in communication systems.

[1]  D. Levy,et al.  Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise , 1972, IEEE Trans. Commun..

[2]  J. Holmes,et al.  Performance of a First-Order Transition Sampling Digital Phase-Locked Loop Using Random-Walk Models , 1972, IEEE Trans. Commun..

[3]  S. Mori,et al.  Performance of Binary Quantized All Digital Phase-Locked Loop with a New Class of Sequential Filter , 1978, IEEE Trans. Commun..

[4]  A. Payzin.  Analysis of a Digital Bit Synchronizer , 1983, IEEE Trans. Commun..

[5]  Keshab K. Parhi.  High-speed architectures for algorithms with quantizer loops , 1990, IEEE International Symposium on Circuits and Systems.

[6]  J.H. Winters,et al.  Techniques for High-Speed Implementation of Nonlinear Cancellation , 1991, IEEE J. Sel. Areas Commun..

[7]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[8]  Masoud Salehi,et al.  Communication Systems Engineering , 1994 .

[9]  Ian Galton.  Analog-input digital phase-locked loops for precise frequency and phase demodulation , 1995 .

[10]  N. C. Beaulieu,et al.  The use of second order Markov chains to model digital symbol synchroniser performance , 1996 .

[11]  Chih-Kong Ken Yang,et al.  A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links , 1996 .

[12]  R. Walker,et al.  A 2.488 Gb/s Si-bipolar clock and data recovery IC with robust loss of signal detection , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[13]  W.J. Dally,et al.  Transmitter equalization for 4-Gbps signaling , 1997, IEEE Micro.

[14]  Deog-Kyoon Jeong,et al.  1.04 GBd low EMI digital video interface system using small swing serial link technique , 1998 .

[15]  P. Batra,et al.  A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[16]  Paul J. Hurst,et al.  An analog DFE for disk drives using a mixed-signal integrator , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[17]  W. Ellersick,et al.  GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[18]  T. Lee,et al.  A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[19]  Changsik Yoo,et al.  A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM , 1999 .

[20]  A. Demir,et al.  Phase noise in oscillators: a unifying theory and numerical methods for characterization , 2000 .

[21]  W. Ellersick,et al.  A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[22]  K. Azadet,et al.  A pipelined 14-tap parallel decision-feedback decoder for 1000BASE-T Gigabit Ethernet , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[23]  A. Hajimiri,et al.  Noise in phase-locked loops , 2001, 2001 Southwest Symposium on Mixed-Signal Design (Cat. No.01EX475).

[24]  Chih-Kong Ken Yang,et al.  Jitter optimization based on phase-locked loop design parameters , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[25]  R. Mooney,et al.  An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[26]  T.P. Thomas,et al.  Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[27]  Un-Ku Moon,et al.  An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 /spl mu/m CMOS , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[28]  H. De Man,et al.  Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[29]  Vladimir Stojanovic,et al.  Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell , 2003 .

[30]  V. Stojanovic,et al.  Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[31]  Gu-Yeon Wei,et al.  An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS , 2003 .