Improving functional verification of embedded systems using hierarchical composition and set theory

During functional verification, complex interactions between multiple modules that compose a digital circuit design can reveal hard-to-find bugs. Functional coverage specifications must be precise to assure these interactions occur during the simulation. We are proposing a technique for improving the functional verification specification of individual modules, preserving the occurrence of these interactions scenarios in the composition phase. We obtain these new specifications in a deductive way, by means of set theory. Using experimental results, we show how our work can contribute to error detection and save functional verification time.

[1]  Janick Bergeron,et al.  Writing Testbenches using SystemVerilog , 2006 .

[2]  Yvon Savaria,et al.  A methodology for validating digital circuits with mutation testing , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[3]  Auri Marcelo Rizzo Vincenzi,et al.  Proteum: a family of tools to support specification and program testing based on mutation , 2001 .

[4]  Ian G. Harris,et al.  A Coverage Metric for the Validation of Interacting Processes , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[5]  Andrew Piziali,et al.  Functional verification coverage measurement and analysis , 2004 .

[6]  Jacob A. Abraham,et al.  Abstraction Techniques for Validation Coverage Analysis and Test Generation , 1998, IEEE Trans. Computers.

[7]  Vincent Beroulle,et al.  Functional Verification of RTL Designs driven by Mutation Testing metrics , 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

[8]  Avi Ziv,et al.  Coverage directed test generation for functional verification using Bayesian networks , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  Mark Horowitz,et al.  Validation coverage analysis for complex digital designs , 1996, Proceedings of International Conference on Computer Aided Design.

[10]  Elmar U. K. Melcher,et al.  A methodology aimed at better integration of functional verification and RTL design , 2005, Des. Autom. Embed. Syst..

[11]  Wolfgang Roesner,et al.  Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) , 2005 .

[12]  Richard J. Lipton,et al.  Theoretical and empirical studies on using program mutation to test the functional correctness of programs , 1980, POPL '80.

[13]  Wolfgang Roesner,et al.  Comprehensive Functional Verification: The Complete Industry Cycle , 2005 .