Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip
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[1] Marc Tremblay,et al. The first MAJC microprocessor: a dual CPU system-on-a-chip , 2001 .
[2] Duo Sheng,et al. Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops , 2000, IEEE Journal of Solid-State Circuits.
[3] Larry L. Biro,et al. Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[4] Manish Gupta,et al. Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors , 2000, IEEE Micro.
[5] Hiroshi Kawaguchi,et al. A reduced clock-swing flip-flop (RCSFF) for 63% power reduction , 1998, IEEE J. Solid State Circuits.
[6] N. Nedovic,et al. Hybrid latch flip-flop with improved power efficiency , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).
[7] Vojin G. Oklobdzija,et al. Conditional techniques for low power consumption flip-flops , 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).
[8] F. Klass. Semi-dynamic and dynamic flip-flops with embedded logic , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[9] Nogawa,et al. A Data-transition Look-ahead DFF Circuit For Statistical Reduction In Power Consumption , 1997 .
[10] Gronowski. Designing High Performance Microprocessors , 1997, Symposium 1997 on VLSI Circuits.
[11] Malgorzata Marek-Sadowska,et al. Low-power buffered clock tree design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] E. You,et al. A third-generation SPARC V9 64-b microprocessor , 2000, IEEE Journal of Solid-State Circuits.
[13] S. S. Rofail,et al. Altering transistor positions: impact on the performance and power dissipation of dynamic latches and flip-flops , 1999 .
[14] Vojin G. Oklobdzija,et al. Dynamic flip-flop with improved power , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[15] Y. Suzuki,et al. Clocked CMOS calculator circuitry , 1973 .
[16] Bai-Sun Kong,et al. Conditional-capture flip-flop technique for statistical power reduction , 2000 .
[17] James Tschanz,et al. Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.
[18] P.P. Gelsinger,et al. Microprocessors for the new millennium: Challenges, opportunities, and new frontiers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[19] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[20] Kawaguchi,et al. A Reduced Clock-swing Flip-flop (RCSFF) For 63% Clock Power Reduction , 1997, Symposium 1997 on VLSI Circuits.
[21] Sung-Mo Kang,et al. A low-swing clock double-edge triggered flip-flop , 2001, VLSIC 2001.
[22] Roland A. Bechade,et al. A 32b 66 MHz 1.8 W microprocessor , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[23] Nogawa,et al. A Data-transition Look-ahead DFF Circuit For Statistical Reduction In Power Consumption , 1997, Symposium 1997 on VLSI Circuits.
[24] Vojin G. Oklobdzija,et al. Timing characterization of dual-edge triggered flip-flops , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.
[25] Shigeya Tanaka,et al. A multi-cycle operational signal processing core for an adaptive equalizer for magnetic system application , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.
[26] Hector Sanchez,et al. A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .
[27] Vladimir Stojanovic,et al. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.
[28] Razak Hossain,et al. Low power design using double edge triggered flip-flops , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[29] Martin D. F. Wong,et al. An efficient and optimal algorithm for simultaneous buffer and wire sizing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[30] R. Allmon,et al. High-performance microprocessor design , 1998, IEEE J. Solid State Circuits.
[31] Robert W. Brodersen,et al. Analysis and design of low-energy flip-flops , 2001, ISLPED '01.
[32] F. Weber,et al. Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[33] Satoshi Tanaka,et al. Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.
[34] Kenneth C. Yeager,et al. 200-MHz superscalar RISC microprocessor , 1996, IEEE J. Solid State Circuits.
[35] A. Gago,et al. Reduced implementation of D-type DET flip-flops , 1993 .
[36] Pong-Fei Lu,et al. Physical design of a fourth-generation POWER GHz microprocessor , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[37] Young-Su Kwon,et al. A new single-clock flip-flop for half-swing clocking , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).
[38] Eby G. Friedman,et al. Repeater design to reduce delay and power in resistive interconnect , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[39] K. Soumyanath,et al. Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/ , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).