Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack

We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density of through silicon vias (TSVs) that may be available, it is possible to connect the FPGA to the die under test through a very high bandwidth connection that can feed multiple short scan chains. We propose and evaluate two designs that exploit the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns, reducing the FPGA resources required and the switching activity in the circuit under test when compared to a more traditional on-chip decompressor implemented to feed short scan chains. For the largest circuit we studied, the switching activity was reduced about 80% and the test time by 90%.

[1]  Kevin A. Kwiat,et al.  Empirical bounds on fault coverage loss due to LFSR aliasing , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[2]  Xilinx Family.  Efficient Shift Registers, LFSR Counters, and Long Pseudo- Random Sequence Generators , 1996 .

[3]  Nilanjan Mukherjee,et al.  Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.

[4]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique for test cost reduction , 2002, Proceedings. International Test Conference.

[5]  Rohit Kapur,et al.  Bounded Adjacent Fill for Low Capture Power Scan Testing , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[6]  Xiaoxia Wu,et al.  Scan-chain design and optimization for three-dimensional integrated circuits , 2009, JETC.

[7]  J. Lau,et al.  Thermal management of 3D IC integration with TSV (through silicon via) , 2009, 2009 59th Electronic Components and Technology Conference.

[8]  Raimund Ubar,et al.  Fast extended test access via JTAG and FPGAs , 2009, 2009 International Test Conference.

[9]  Patrick Dorsey.  Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency , 2010 .

[10]  Walter Stechele,et al.  Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems , 2010, ARC.

[11]  John Park.  Thinking outside of the chip , 2010, ISPD '10.

[12]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[13]  Vivek Chickermane,et al.  DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks , 2012, 2012 IEEE International Test Conference.

[14]  Bruno Rouzeyre,et al.  A JTAG based 3D DfT architecture using automatic die detection , 2013, Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

[15]  Ajay Khoche,et al.  FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System , 2013, IEEE Design & Test.

[16]  Krishnendu Chakrabarty,et al.  Test-cost optimization and test-flow selection for 3D-stacked ICs , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[17]  Payel Ghosh,et al.  Session Based Core Test Scheduling for 3D SOCs , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[18]  Jun Zhou,et al.  BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Sergei Devadze,et al.  Virtual reconfigurable scan-chains on FPGAs for optimized board test , 2015, 2015 16th Latin-American Test Symposium (LATS).

[20]  Yi Sun,et al.  Using Existing Reconfigurable Logic in 3D Die Stacks for Test , 2016, 2016 IEEE 25th North Atlantic Test Workshop (NATW).

[21]  Xiaowu Zhang,et al.  Heat Dissipation Enhancement of 2.5D Package with 3D Graphene and 3D Boron Nitride Networks as Thermal Interface Material (TIM) , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[22]  Vivek Chickermane,et al.  Advancing test compression to the physical dimension , 2017, 2017 IEEE International Test Conference (ITC).

[23]  Chongshen Song,et al.  A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[24]  Howard Eisner.  Thinking outside the box , 2019 .