A fresh look at majority multiplexing when devices get into the picture

In this paper we present the first detailed analysis of von Neumann multiplexing (vN-MUX) using majority (MAJ) gates of small fan-ins Delta (MAJ-Delta) with respect to the probability of failure of the elementary (nano-)devices. Only gates with small fan-ins have been considered, as gates with large fan-ins do not seem practical (at least in the short term) in future technologies. The extensions from an exact counting algorithm (for gate defects and faults only) to device-level failures will allow us to estimate and characterize MAJ-Delta vN-MUX with respect to device-level malfunctions. The reported results depart significantly from all known gate-level analyses-either theoretical or based on simulations. These should be quite important as providing a detailed picture of the behavior of MAJ-Delta vN-MUX when considering the (unreliability of the elementary) (nano-)devices (as opposed to gate-level only analyses). The main conclusion is that small fan-in gates (and redundancy schemes relying on such gates) are quite promising-in spite of all previous results at gate-level showing the contrary.

[1]  Valeriu Beiu,et al.  What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details , 2007, IWANN.

[2]  Hao Yan,et al.  DNA tile based self-assembly: building complex nanoarchitectures. , 2006, Chemphyschem : a European journal of chemical physics and physical chemistry.

[3]  Theresa F. Klaschka.  A Method for Redundancy Scheme Performance Assessment , 1971, IEEE Transactions on Computers.

[4]  M. Forshaw,et al.  Architectures for reliable computing with unreliable nanodevices , 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

[5]  Sarita V. Adve,et al.  The impact of technology scaling on lifetime reliability , 2004, International Conference on Dependable Systems and Networks, 2004.

[6]  Sarita V. Adve,et al.  AS SCALING THREATENS TO ERODE RELIABILITY STANDARDS, LIFETIME RELIABILITY MUST BECOME A FIRST-CLASS DESIGN CONSTRAINT. MICROARCHITECTURAL INTERVENTION OFFERS A NOVEL WAY TO MANAGE LIFETIME RELIABILITY WITHOUT SIGNIFICANTLY SACRIFICING COST AND PERFORMANCE , 2005 .

[7]  Way Kuo.  Challenges Related to Reliability in Nano Electronics , 2006 .

[8]  J. E. Brewer,et al.  Extending the road beyond CMOS , 2002 .

[9]  J. Neumann.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[10]  George R. Roelke,et al.  Analytical Models for the Performance of von Neumann Multiplexing , 2007, IEEE Transactions on Nanotechnology.

[11]  V. Beiu,et al.  Accurate Nano-Circuits Reliability Evaluations Based on Combining Numerical Simulations with Monte Carlo , 2007, 2007 2nd International Design and Test Workshop.

[12]  Sarita V. Adve,et al.  Lifetime reliability aware microprocessors , 2006 .

[13]  Valeriu Beiu,et al.  Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

[14]  Christof M. Niemeyer,et al.  Rational Design of DNA Nanoarchitectures , 2006 .

[15]  Konstantin K. Likharev,et al.  Single-electron devices and their applications , 1999, Proc. IEEE.

[16]  V. Beiu,et al.  On Practical Multiplexing Issues , 2006, 2006 Sixth IEEE Conference on Nanotechnology.

[17]  Bonnie A. Sheriff,et al.  A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre , 2007, Nature.

[18]  Leonard J. Schulman,et al.  On the maximum tolerable noise of k-input gates for reliable computation by formulas , 2003, IEEE Trans. Inf. Theory.

[19]  J. Peabody.  Application of Fault Tolerance to Interactive Music , 2003 .

[20]  Valeriu Beiu,et al.  Gate Failures Effectively Shape Multiplexing , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[21]  S. Roy,et al.  Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures , 2005, IEEE Transactions on Nanotechnology.

[22]  A. S. Sadek,et al.  Parallel information and computation with restitution for noise-tolerant nanoscale logic networks , 2003 .

[23]  Sixth Framework Programme.  A Review of the Status of Research and Training into Architectures for Nanoelectronic and Nanophotonic Systems in the European Research Area , 2004 .

[24]  Arthur Nieuwoudt,et al.  Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits , 2006, JETC.

[25]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[26]  L. Schulman,et al.  Information theory and noisy computation , 1995, Proceedings of 1995 IEEE International Symposium on Information Theory.

[27]  Jie Han,et al.  A system architecture solution for unreliable nanoelectronic devices , 2002 .

[28]  A. S. Sadek,et al.  Fault-tolerant techniques for nanocomputers , 2002 .

[29]  U. Ruckert,et al.  On nanoelectronic architectural challenges and solutions , 2004, 4th IEEE Conference on Nanotechnology, 2004..