Analysis and Mitigation of Common Mode Current in SiC MOSFET Gate Driver Power Supply

High dv/dt and di/dt pose new challenges to the gate driver design of Silicon Carbide (SiC) power devices. High voltage insulation and electromagnetic inference (EMI) design considerations related to the gate driver designs must be well thought-out in order to ensure the safety and proper functionality of the gate driver power supply. This paper presents an analysis of the common-mode (CM) propagation paths within the gate driver power supply. The parasitic impedances subject to CM current in a half-bridge topology gate driver architecture are analyzed and an equivalent circuit model is developed. In addition, several mitigation approaches, including common-mode choke, balancing, and serial connection of power supplies to minimize the CM current. These techniques used in this gate driver architecture are validated analytically as well as through simulation.