High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling
暂无分享,去创建一个
[1] Michitaka Kameyama,et al. Bidirectional data transfer based asynchronous VLSI system using multiple-valued current mode logic , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..
[2] A. Katoch,et al. Fast signal propagation for point to point on–chip long interconnects using current sensing , 2002, Proceedings of the 28th European Solid-State Circuits Conference.
[3] Ethiopia Nigussie,et al. Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).
[4] Hannu Tenhunen,et al. Repeater insertion to minimise delay in coupled interconnects , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[5] Mattan Kamon,et al. FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.
[6] Ron Ho,et al. Long wires and asynchronous control , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..
[7] S. I. Long,et al. Low power current mode multi-valued logic interconnect for high speed interchip communications , 1995, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995.
[8] Turgay Temel,et al. Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits , 2004 .
[9] Yehea I. Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[10] Larry L. Biro,et al. Power considerations in the design of the Alpha 21264 microprocessor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[11] Jae-Yoon Sim,et al. A 1-Gb/s bidirectional I/O buffer using the current-mode scheme , 1999 .
[12] Kurt Keutzer,et al. A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] Tom Verhoeff,et al. Delay-insensitive codes — an overview , 1988, Distributed Computing.
[14] Yehea Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1999 .
[15] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[16] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[17] William J. Dally,et al. Digital systems engineering , 1998 .
[18] Harry J. M. Veendrick,et al. High speed current-mode signaling circuits for on-chip interconnects , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[19] James D. Meindl,et al. Compact distributed RLC interconnect models - part IV: unified models for time delay, crosstalk, and repeater insertion , 2003 .
[20] A. R. Djordjević. LINPAR for Windows : matrix parameters for multiconductor transmission lines : software and user's manual, version 2.0 , 1999 .
[21] Rizwan Bashirullah. Reduced delay sensitivity to process induced variability in current sensing interconnects , 2006 .
[22] M. Gail Jones,et al. It's a Small World After All. , 2005 .
[23] A. Jose,et al. Near speed-of-light on-chip interconnects using pulsed current-mode signalling , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..
[24] Mohammed Ismail,et al. Current mode, low-power, on-chip signaling in deep-submicron CMOS technology , 2003 .
[25] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[26] Wentai Liu,et al. Current-mode signaling in deep submicrometer global interconnects , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[27] Radu Marculescu,et al. "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[28] Wayne P. Burleson,et al. Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations , 2005, Sixth international symposium on quality electronic design (isqed'05).
[29] Mattan Kamon,et al. FASTHENRY: a multipole-accelerated 3-D inductance extraction program , 1994 .