A multi-objective approach for software/hardware partitioning in a multi-target tracking system

Heterogeneous Multiprocessor System-on-Chips (MPSoCs) are getting increasingly used to cope with new embedded applications performance requirements. In such systems, the promising cohabitation of processing elements (PEs) having different aspects allows designers to better exploit the synergy of hardware and software cores. Software/Hardware partitioning investigates the design of MPSOCs to take advantage of software flexibility and hardware high performance with the lowest possible costs. Signal-processing-oriented systems handle huge amounts of data and consequently demand highly performant architecture. In this paper, we propose a Software/Hardware partitioning approach for high speed reconfigurable DSP-oriented embedded systems. We present two multi-objective techniques aiming at exploring the partitioning configurations that minimize execution time, resource utilization and time to market of the MPSoC.

[1]  Mohamed B. Abdelhalim,et al.  Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization Technique , 2007, IESS.

[2]  Yassin Elhillali,et al.  An MPSoC architecture for the Multiple Target Tracking application in driver assistant system , 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

[3]  Mouloud Koudil,et al.  Solving Partitioning Problem in Codesign with Ant Colonies , 2005, IWINAC.

[4]  Lanying Li,et al.  Hardware/Software Partitioning Based on Hybrid Genetic and Tabu Search in the Dynamically Reconfigurable System , 2015 .

[5]  H. Ishibuchi,et al.  Multi-objective genetic local search for minimizing the number of fuzzy rules for pattern classification problems , 1998, 1998 IEEE International Conference on Fuzzy Systems Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98CH36228).

[6]  Lothar Thiele,et al.  Multiobjective evolutionary algorithms: a comparative case study and the strength Pareto approach , 1999, IEEE Trans. Evol. Comput..

[7]  Nikil D. Dutt,et al.  Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Pierre Hansen,et al.  Variable Neighborhood Search , 2018, Handbook of Heuristics.

[9]  Giovanni Beltrame,et al.  A comparative evaluation of multi-objective exploration algorithms for high-level design , 2014, TODE.

[10]  Rudy Lauwereins,et al.  ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.

[11]  Kia Bazargan,et al.  HW/SW codesign incorporating edge delays using dynamic programming , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[12]  Roberto Cordone,et al.  Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Smaïl Niar,et al.  ARABICA: A Reconfigurable Arithmetic Block for ISA Customization , 2014, ARC.

[14]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[15]  Wu Jigang,et al.  Low-complex dynamic programming algorithm for hardware/software partitioning , 2006, Inf. Process. Lett..

[16]  Mohamed Abid,et al.  Design Space Exploration for Customized Asymmetric Heterogeneous MPSoC , 2014, 2014 17th Euromicro Conference on Digital System Design.