Unbiased estimation of linewidth roughness

Linewidth roughness (LWR) is usually estimated simply as three standard deviations of the linewidth. The effect of image noise upon this metric includes a positive nonrandom component. The metric is therefore subject to a bias or "systematic error" that we have estimated can be comparable in size to the roughness itself for samples as smooth as required by the industry roadmap. We illustrate the problem using scanning electron microscope images of rough lines. We propose simple changes to the measurement algorithm that, if adopted by metrology instrument suppliers, would permit estimation of LWR without bias caused by image noise.

[1]  Michael T. Postek,et al.  A Simulation Study of Repeatability and Bias in the CD-SEM | NIST , 2003 .

[2]  John S. Villarrubia,et al.  CD-SEM measurement line edge roughness test patterns for 193 nm lithography , 2003, SPIE Advanced Lithography.

[3]  John S. Villarrubia,et al.  Determination of optimal parameters for CD-SEM measurement of line-edge roughness , 2004, SPIE Advanced Lithography.

[4]  Atsuko Yamaguchi,et al.  Metrology of LER: influence of line-edge roughness (LER) on transistor performance , 2004, SPIE Advanced Lithography.

[5]  Michael T. Postek,et al.  Simulation study of repeatability and bias in the CD-SEM , 2003, SPIE Advanced Lithography.

[6]  Vladimir A. Ukraintsev Effect of bias variation on total uncertainty of CD measurements , 2003, SPIE Advanced Lithography.

[7]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[8]  Shiying Xiong,et al.  Gate line-edge roughness effects in 50-nm bulk MOSFET devices , 2002, SPIE Advanced Lithography.

[9]  Michael T. Postek,et al.  Scanning electron microscope dimensional metrology using a model‐based library , 2005 .

[10]  C.H. Diaz,et al.  An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.

[11]  A. Asenov,et al.  Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .

[12]  Atsuko Yamaguchi,et al.  Characterization of line-edge roughness in resist patterns and estimations of its effect on device performance , 2003, SPIE Advanced Lithography.