SESAM: An MPSoC Simulation Environment for Dynamic Application Processing

Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase in the design complexity of MPSoC architectures that must support these constraints, flexible and accurate simulators become a necessity for exploring the vast design space solutions. In this paper, we present an asymmetric MPSoC simulator environment, named SESAM. This tool can be used for the architecture exploration and optimization, and the design of a complete MPSoC solution for dynamic application processing. Its performances and capabilities are demonstrated through a complete MPSoC platform and an implementation of the component labeling algorithm.

[1]  Lionel Lacassagne,et al.  Light speed labeling: efficient connected component labeling on RISC architectures , 2011, Journal of Real-Time Image Processing.

[2]  David J. Lilja,et al.  Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations , 2006, IEEE Transactions on Computers.

[3]  Kenji Suzuki,et al.  Linear-time connected-component labeling based on sequential local operations , 2003, Comput. Vis. Image Underst..

[4]  Chun-Jen Chen,et al.  A linear-time component-labeling algorithm using contour tracing technique , 2004, Comput. Vis. Image Underst..

[5]  Jason Cong,et al.  MC-Sim: an efficient simulation tool for MPSoC designs , 2008, ICCAD 2008.

[6]  Nicolas Ventroux,et al.  Towards a parameterizable cycle-accurate ISS in ArchC , 2010, ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010.

[7]  Wayne H. Wolf,et al.  Multiprocessor Systems-on-Chips , 2004, ISVLSI.

[8]  Giuseppe Lipari,et al.  Schedulability Analysis of Global Scheduling Algorithms on Multiprocessor Platforms , 2009, IEEE Transactions on Parallel and Distributed Systems.

[9]  Rodolfo Azevedo,et al.  The ArchC Architecture Description Language and Tools , 2005, International Journal of Parallel Programming.

[10]  Nicolas Ventroux,et al.  Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[11]  Luca Benini,et al.  MPARM: Exploring the Multi-Processor SoC Design Space with SystemC , 2005, J. VLSI Signal Process..

[12]  Luca Fossati,et al.  ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration , 2008, 2008 Asia and South Pacific Design Automation Conference.

[13]  Brian Foote,et al.  Reflective facilities in Smalltalk-80 , 1989, OOPSLA 1989.