A Low-Overhead BIST Architecture for Digital Data Processing Circuits
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[1] Ted Painter,et al. Audio Signal Processing and Coding , 2007 .
[2] Janusz Rajski,et al. Test responses compaction in accumulators with rotate carry adders , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Charles E. Stroud,et al. On Built-In Self-Test for Adders , 2009, J. Electron. Test..
[4] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[5] Dimitris Nikolos,et al. On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Vladimir Britanak,et al. A new fast algorithm for the unified forward and inverse MDCT/MDST computation , 2002, Signal Process..
[7] Hans-Joachim Wunderlich,et al. Efficient Concurrent Self-Test with Partially Specified Patterns , 2010, J. Electron. Test..
[8] Sarita Thakar,et al. On the generation of test patterns for combinational circuits , 1993 .
[9] Witold A. Pleskacz,et al. MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio , 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.
[10] S. Kuo,et al. Design-for-Testability Techniques for Arithmetic Circuits , 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.