MORPHEUS: Exploitation of Reconfiguration for Increased Run-Time Flexibility and Self-Adaptive Capabilities in Future SoCs

The exponential increase of CMOS circuit complexity has opened the way to the introduction of new capabilities and functionalities into electronic systems that have been sources of innovations in major growth markets. To pursue this trend all along the last decades, major evolutions of design methodologies and ­computing architectures have been necessaries to master this complexity. Now, increasing Non-Recurrent Engineering (NRE) costs have made the design of ASICs or System-on-Chips unaffordable for a broad class of applications, whose the low-volume markets are insufficient to make them economically viable. But, use of Commercial Off-The-Shelf (COTS) boards is not always satisfactory due to the low power-efficiency of general-purpose processors and the complexity of programming FPGAs. We thus advocate for a new class of System-on-Chips, composed of a mix of processors as well as very flexible and easily programmable accelerators in order to cope with increasing NRE costs and tight time-to-markets. In this perspective, reconfigurable architectures are very appealing for their trade-off between the performance of ASICs and the flexibility of general-purpose processors. This chapter presents an innovative approach of a dynamically reconfigurable heterogeneous platform, called MORPHEUS and which consists of a System-on-Chip integrating different kinds of reconfigurable accelerators controlled by a general-purpose processor.