A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic

For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at http://www.ens-lyon.fr/LIP/Arenaire/.

[1]  Fred J. Taylor,et al.  A 20 Bit Logarithmic Number System Processor , 1988, IEEE Trans. Computers.

[2]  David M. Lewis.  An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System , 1990, IEEE Trans. Computers.

[3]  David Goldberg,et al.  What every computer scientist should know about floating-point arithmetic , 1991, CSUR.

[4]  David Goldberg.  What Every Computer Scientist Should Know About Floating-Point Arithmetic , 1992 .

[5]  M. Ercegovac,et al.  Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .

[6]  Vassilis Paliouras,et al.  A novel algorithm for accurate logarithmic number system subtraction , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[7]  Liang-Gee Chen,et al.  A 32-bit logarithmic number system processor , 1996, J. VLSI Signal Process..

[8]  Mark G. Arnold,et al.  Arithmetic co-transformations in the real and complex logarithmic number systems , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[9]  Mark G. Arnold,et al.  Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems , 1998, IEEE Trans. Computers.

[10]  Jirí Kadlec,et al.  Arithmetic on the European Logarithmic Microprocessor , 2000, IEEE Trans. Computers.

[11]  Arnaud Tisserand,et al.  Some improvements on multipartite table methods , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[12]  Michael J. Flynn,et al.  Advanced Computer Arithmetic Design , 2001 .

[13]  Pavle Belanovic,et al.  A Library of Parameterized Floating-Point Modules and Their Use , 2002, FPL.

[14]  Jirí Kadlec,et al.  Logarithmic Number System and Floating-Point Arithmetics on FPGA , 2002, FPL.

[15]  N. Burgess,et al.  Parameterisable floating-point operations on FPGA , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[16]  Brent E. Nelson,et al.  Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture , 2002, FPL.

[17]  Reinhard Männer,et al.  Using floating-point arithmetic on FPGAs to accelerate scientific N-Body simulations , 2002, Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[18]  Arnaud Tisserand,et al.  Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices , 2002, FPL.

[19]  Wayne Luk,et al.  Automating Customisation of Floating-Point Designs , 2002, FPL.

[20]  Yvon Savaria,et al.  A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs , 2002, FPGA '02.

[21]  J. Detrey,et al.  A VHDL library of LNS operators , 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

[22]  Neil Burgess,et al.  A Dual-Path Logarithmic Number System Addition/Subtraction Scheme for FPGA , 2003, FPL.

[23]  A Study on the Design of Floating-Point Functions in FPGAs , 2003, FPL.

[24]  Christopher C. Doss,et al.  FPGA-based implementation of a robust IEEE-754 exponential unit , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[25]  Florent de Dinechin,et al.  Second Order Function Approximation Using a Single Multiplication on FPGAs , 2004, FPL.

[26]  Tomás Lang,et al.  Digit-Serial Arithmetic , 2004 .

[27]  Karl S. Hemmert,et al.  A comparison of floating point and logarithmic number systems for FPGAs , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[28]  Yong Dou,et al.  64-bit floating-point FPGA matrix multiplication , 2005, FPGA '05.

[29]  André DeHon,et al.  Floating-point sparse matrix-vector multiply for FPGAs , 2005, FPGA '05.

[30]  Harald Haas,et al.  Asilomar Conference on Signals, Systems, and Computers , 2006 .

[31]  Milos D. Ercegovac,et al.  Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.