A Spanning Tree Carry Lookahead Adder
暂无分享,去创建一个
[1] Martine D. F. Schlag,et al. Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip , 1990, IEEE Trans. Computers.
[2] Joseph Cavanagh,et al. Digital Computer Arithmetic , 1983 .
[3] M. Lehman,et al. Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units , 1961, IRE Trans. Electron. Comput..
[4] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[5] Earl E. Swartzlander,et al. The redundant cell adder , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.
[6] G. De Micheli,et al. Approaching a nanosecond: a 32 bit adder , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[7] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[8] Orest J. Bedrij. Carry-Select Adder , 1962, IRE Trans. Electron. Comput..
[9] Vojin G. Oklobdzija,et al. Delay optimization of carry-skip adders and block carry-lookahead adders , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.
[10] Huey Ling. High Speed Binary Adder , 1981, IBM J. Res. Dev..
[11] Tack-Don Han,et al. Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).
[12] T. Kilburn,et al. Parallel addition in digital computers: a new fast 'carry' circuit , 1959 .