The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits
暂无分享,去创建一个
[1] Todd J. Wagner. Hierarchical Layout Verification , 1985, IEEE Design & Test of Computers.
[2] W. Meier. Hierarchical layout verification for submicron designs , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[3] Michael H Arnold. Corner-Based Geometric Layout Rule Checking for VLSI Circuits , 1985 .
[4] Ludo Weyten,et al. Quad list quad trees: a geometrical data structure with improved performance for large region queries , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Kjell Jeppson,et al. A parallel hierarchical design rule checker , 1992, [1992] Proceedings The European Conference on Design Automation.
[6] Kjell O. Jeppson,et al. Formal definitions of edge-based geometric design rules , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] John K. Ousterhout,et al. Lyra: A New Approach to Geometric Layout Rule Checking , 1982, DAC 1982.
[8] A. R. Newton,et al. Electronic CAD Frameworks , 1992 .
[9] George S. Taylor,et al. Magic's Incremental Design-Rule Checker , 1984, 21st Design Automation Conference Proceedings.
[10] Kjell O. Jeppson,et al. New algorithms for increased efficiency in hierarchical design rule checking , 1987, Integr..
[11] Kjell O. Jeppson,et al. The Use of Inverse Layout Trees for Hierarchical Design Rule Checking , 1989, 26th ACM/IEEE Design Automation Conference.
[12] Kjell O. Jeppson,et al. The use of inverse layout trees for hierarchical design verification , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[13] Randy Lee Brown. Multiple Storage Quad Trees: A Simpler Faster Alternative to Bisector List Quad Trees , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Louis K. Scheffer,et al. Hierarchical Analysis of IC Artwork with User Defined Abstraction Rules , 1985, DAC 1985.