Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications

A nonvolatile processor based on three-terminal cells provides a leakage current under 20 nA and a software-controlled backup/restore for system state. Newly introduced CPU instruction and logging mode enable the peak current to relax during writing. The processor using a power gating with a 10-kHz effective frequency provides a 97% reduction in power consumption compared to that of when there is no power management.