An improved method for delay fault testing of NoC interconnections

Testing of chips built using deep sub-micron technology is becoming harder since crosstalk and small variations in the fabrication processes are adversely affecting circuit dynamic behaviour. The resulting logic and delay faults can only be detected using at-speed testing of the circuits. Faults resulting from crosstalk become more prominent among long links connecting two clock domains in a system designed using Globally Asynchronous Locally Synchronous (GALS) principles. We propose an efficient method for at-speed testing of delay faults in links used for handshaking based communication among GALS domains. The proposed method is conservative in the sense that it can detect all delay faults in links but may also label some good chips as faulty with a small probability. It is possible to extend the proposed method to combine it with functional testing of the link and adapt it for on-line testing A typical handshaking protocol uses two control lines, Write and Ready To Receive (RTR). clock-generator The more difficult to detect and in many cases more dangerous fault is if a defect makes a data line more delayed than the signal Write. We present a method for detection of such delay faults. This figure shows the clock at the receiver along with signal Write and the data lines. T R is the clock period time at the receiver and t l is the time from the data arrives until Write arrives at the receiver. If t l is negative a delay fault exists that might result in erroneous data To detect if a delay fault is present, test data is sent by the transmitter. The receiver reads the data both on its active clock edge just before and on its active clock edge just after signal Write has arrived. If the data is correct at the first read it implies that t l > 0 and then the delay fault we are looking for is not present. If the data is erroneous at the second read, there is a fault. If non of these two cases occurs, then this instance of the test could not judge if the fault is present or not. In the presented algorithm this test experiment is repeated until it can be judged if the fault is present or not, or until a certain number of repetitions is made. Appropriate test patterns are put on the data line to cause worst case delay. To achieve this, …