Microelectronic architectures and devices for signal and symbol processing

Modern microelectronics technology holds the promise of high level, computer-aided design of very complex systems on a single silicon chip. The freedom to create non-standard architectures within this context has stimulated widespread interest in the development of computing structures that offer increased processing speed relative to the von Neumann architecture. This paper describes two architectures that are especially well suited for large scale integration because of their concurrent structure and their use of primarily local data flows. The first architecture is designed to implement the QR matrix decomposition and it can be used to reliably solve the least squares and eigenvalue problems of linear algebra. The second architecture is based on an elementary building block approach to the realization of FIR and IIR lattice digital filters. An especially important issue that is sometimes overlooked in the system level design of an architecture is the impact of the particular scheme for implementing the fundamental operations such as multiplication, rotation, etc., on the performance of the highly parallel computing structure. It is argued that if one can imbed pipelined operations within the concurrent computing structure, then often the resulting system will not only provide substantial processing gain but it can be implemented in such a way that efficient use of chip real estate is achieved.