Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform

This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.

[1]  Satoshi Takaya,et al.  7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Kaushik Roy,et al.  A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited , 2017, DAC.

[3]  Hitoshi Kubota,et al.  Tunnel Magnetoresistance above 170% and Resistance–Area Product of 1 Ω (µm)2 Attained by In situ Annealing of Ultra-Thin MgO Tunnel Barrier , 2011 .

[4]  Kamalika Datta,et al.  Modelling and Simulation of Non-Ideal MAGIC NOR Gates on Memristor Crossbar , 2018, 2018 8th International Symposium on Embedded Computing and System Design (ISED).

[5]  Sachin S. Sapatnekar,et al.  In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping , 2019, IEEE Transactions on Computers.

[6]  Sachin S. Sapatnekar,et al.  Spin-Based Computing: Device Concepts, Current Status, and a Case Study on a High-Performance Microprocessor , 2015, Proceedings of the IEEE.

[7]  Sachin S. Sapatnekar,et al.  Efficient In-Memory Processing Using Spintronics , 2018, IEEE Computer Architecture Letters.

[8]  Lawrence T. Clark,et al.  Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit , 2017, 2017 IEEE International Conference on Microelectronic Systems Education (MSE).

[9]  Saurabh Sinha,et al.  ASAP7: A 7-nm finFET predictive process design kit , 2016, Microelectron. J..

[10]  Alireza Shafaei,et al.  Low write-energy STT-MRAMs using FinFET-based access transistors , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

[11]  Sachin S. Sapatnekar,et al.  True In-memory Computing with the CRAM: From Technology to Applications , 2019, ACM Great Lakes Symposium on VLSI.

[12]  Sachin S. Sapatnekar,et al.  Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform , 2019, 20th International Symposium on Quality Electronic Design (ISQED).

[13]  Tom Zhong,et al.  Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[14]  Igor Zutic,et al.  Roadmap for Emerging Materials for Spintronic Device Applications , 2015, IEEE Transactions on Magnetics.

[15]  Mohammed A. Zidan,et al.  Parasitic Effect Analysis in Memristor-Array-Based Neuromorphic Systems , 2018, IEEE Transactions on Nanotechnology.