A Power Efficient Image Convolution Engine for Field Programmable Gate Arrays

[1]  A. Berkun,et al.  FPGAs make a radar signal processor on a chip a reality , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[2]  Andrea Prati,et al.  Image convolution on FPGAs: the implementation of a multi-FPGA FIFO structure , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

[3]  B.E. Nelson.  Configurable computing and sonar processing - architectures and implementations , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[4]  Li Shang,et al.  Dynamic power consumption in Virtex™-II FPGA family , 2002, FPGA '02.