An observability enhancement approach for improved testability and at-speed test

Some recent studies show that an at-speed sequential or functional test is better than a test executed at lower speed. Design-for-testability approaches based on full scan, partial scan or silicon-based solutions such as Crosscheck achieve very high stuck-at fault coverage. However, in all these cases, the tests have to be applied at speeds lower than the operation speed of the circuit. In this paper, a design-for-test method that permits at-speed testing is introduced. The method is based on probe point insertion for improved observability, and it requires enhancements to an existing sequential circuit fault simulator. Faults that can be activated but not detected at existing primary outputs are targeted. A minimal set of probe points is selected to detect these faults, and the probe points are compressed to one or two output pins using exclusive-OR trees. The issue of aliasing of fault effects is addressed. Improvements in fault coverage were made for all 17 of the ISCAS89 sequential benchmark circuits studied. Fault coverages between 99% and 100% were obtained for seven circuits, and 100% ATG effectiveness was achieved on all but two circuits. >

[1]  R. Wadsack.  Fault coverage in digital integrated circuits , 1978, The Bell System Technical Journal.

[2]  Balakrishnan Krishnamurthy.  A Dynamic Programming Approach to the Test Point Insertion Problem , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Vishwani D. Agrawal,et al.  An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited , 1990, Proceedings. International Test Conference 1990.

[4]  Irith Pomeranz,et al.  Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[5]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[6]  T. Ghewala.  CrossCheck: A Cell Based VLSI Testability Solution , 1989, DAC.

[7]  Janak H. Patel,et al.  PROOFS: a fast, memory-efficient sequential circuit fault simulator , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Akihiro Yamamoto,et al.  Parity-Scan Design to Reduce the Cost of Test Application , 1992, Proceedings International Test Conference 1992.

[9]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[10]  Elizabeth M. Rudnick,et al.  Non-Scan Design-for-Testability Techniques for Sequential Circuits , 1993, 30th ACM/IEEE Design Automation Conference.

[11]  Daniel Brand,et al.  Synthesis of pseudo-random pattern testable designs , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[12]  Edward J. McCluskey,et al.  IC qualityd and test transparency , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[13]  Arthur D. Friedman,et al.  Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.

[14]  Robert C. Aitken,et al.  THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%? , 1991, 1991, Proceedings. International Test Conference.

[15]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[16]  Prathima Agrawal,et al.  LSI Product Quality and Fault Coverage , 1981, 18th Design Automation Conference.

[17]  Takuji Ogihara,et al.  Test generation for sequential circuits using individual initial value propagation , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[18]  Tushar Gheewala,et al.  ATPG based on a novel grid-addressable latch element , 1991, 28th ACM/IEEE Design Automation Conference.

[19]  Ronald L. Rivest,et al.  Introduction to Algorithms , 1990 .

[20]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[21]  T. Gheewala,et al.  CrossCheck: A Cell Based VLSI Testability Solution , 1989, 26th ACM/IEEE Design Automation Conference.