Optimal Common Subexpression Elimination Algorithm for FIR Filter and Implementation on FPGA

To reduce the consumption of field programmable gate array resources,the horizontal common subexpression elimination algorithm and vertical common subexpression elimination algorithm in designing the FIR filter were studied.Further,an optimal common subexpression elimination algorithm combined the advantages of these two algorithms was presented in this paper so that the operation units can be reduced more efficiently.This paper built a model by using DSP builder firstly to implement a 32-order low-pass FIR filter and then simulated the model with Modelsim and QuartusⅡ.The simulation result shows that the optimal CSE design uses less logic elements and logic depths,and the optimization FIR filter design saves more hardware resources than the direct multiplication method and the distributed method do.Finally,the implementation of designed filter was done on DE2 development board.The result shows that the filtering effect is in keeping with the simulation result.