On the use of distributed reconfigurable hardware in launch control avionics

This paper discusses the feasibility of employing reconfigurable hardware in the avionics systems of future generations of launch vehicles for space. Such technology has the potential of being orders of magnitude faster than conventional embedded computer technology for many applications. It can be argued that avionics architectures that use such reconfigurable elements may vastly improve the flexibility, efficiency, performance and reusability of the avionics system. It can also be argued that such a flexible environment will facilitate the implementation of advanced and mission-specific real-time fault tolerance, avoidance, and corrective techniques and would greatly facilitate sensor/data fusion operations. However, before this technology can be applied to such safety critical applications there are several issues that must be resolved. Such issues center around the suitability and robustness of reconfigurable hardware for in-flight operation. In this paper we investigate many of these issues, focussing upon the use of reconfigurable hardware to form a generic multi-functional launch controller element that can be replicated as needed and distributed throughout the launch vehicle.

[1]  Rajesh Gupta,et al.  Hardware/software co-design , 1996, Proc. IEEE.

[2]  Thomas P. Flatley,et al.  Extending NASA's Data Processing to Spacecraft , 1999, Computer.

[3]  Jih-Jong Wang,et al.  SRAM based re-programmable FPGA for space applications , 1999 .

[4]  Jack S. N. Jean,et al.  Dynamic Reconfiguration to Support Concurrent Applications , 1999, IEEE Trans. Computers.

[5]  Miodrag Potkonjak,et al.  Enhanced FPGA reliability through efficient run-time fault reconfiguration , 2000, IEEE Trans. Reliab..

[6]  Miodrag Potkonjak,et al.  Low overhead fault-tolerant FPGA systems , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Brad Hutchings,et al.  The flexibility of configurable computing , 1998 .

[8]  H.M. Heys,et al.  The FPGA implementation of the RC6 and CAST-256 encryption algorithms , 1999, Engineering Solutions for the Next Millennium. 1999 IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.99TH8411).

[9]  Jörg Henkel,et al.  An approach to the adaptation of estimated cost parameters in the COSYMA system , 1994, CODES '94.

[10]  Kevin J. Paar,et al.  Implementation of a finite difference method on a custom computing platform , 1996, Other Conferences.

[11]  Xiaobo Sharon Hu,et al.  Configuration-level hardware/software partitioning for real-time embedded systems , 1994, CODES.

[12]  Xiaobo Hu,et al.  Configuration-level hardware/software partitioning for real-time embedded systems , 1994, Third International Workshop on Hardware/Software Codesign.

[13]  John Wawrzynek,et al.  Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[14]  I. Xilinx.  Virtex series configuration architecture user guide , 2000 .

[15]  A. El Gamal,et al.  Architecture of field-programmable gate arrays , 1993, Proc. IEEE.

[16]  Anne Elisabeth Haxthausen,et al.  LYCOS: the Lyngby Co-Synthesis System , 1997, Des. Autom. Embed. Syst..

[17]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[18]  Kenneth A. LaBel,et al.  Radiation effects on current field programmable technologies , 1997 .

[19]  Dirk Herrmann,et al.  The Cosyma System , 1997 .

[20]  Wolfram Hardt,et al.  Trade-Offs in HW/SW Codesign , 1996 .

[21]  Tracy Larrabee,et al.  A scalable, loadable custom programmable logic device for solving Boolean satisfiability problems , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).

[22]  Vincenza Carchiolo,et al.  Hardware/software synthesis of formal specifications in codesign of embedded systems , 2000, TODE.

[23]  Diederik Verkest,et al.  Hardware/software co-design of digital telecommunication systems , 1997, Proc. IEEE.

[24]  Neil W. Bergmann,et al.  Adaptive Instrument Module - A Reconfigurable Processor for Spacecraft Applications , 2000 .

[25]  Jean Vuillemin,et al.  Programmable Active Memories: A Performance Assessment , 1992, Heinz Nixdorf Symposium.

[26]  Martin Turner,et al.  An FPGA-based hardware accelerator for image processing , 1994 .

[27]  Scott Hauck,et al.  The roles of FPGAs in reprogrammable systems , 1998, Proc. IEEE.

[28]  Mark Shand.  Flexible image acquisition using reconfigurable hardware , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[29]  Luciano Lavagno,et al.  Intellectual property re-use in embedded system co-design: an industrial case study , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

[30]  Peter Athanas,et al.  Finding lines and building pyramids with SPLASH 2 , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[31]  Axel Jantsch,et al.  Hardware/software partitioning and minimizing memory interface traffic , 1994, EURO-DAC '94.

[32]  Vivek Sarkar,et al.  Baring It All to Software: Raw Machines , 1997, Computer.

[33]  Wolfgang Rosenstiel,et al.  A method for partitioning UNITY language in hardware and software , 1994, EURO-DAC '94.

[34]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[35]  Richard W. Conners,et al.  A MOdular and Reprogrammable Real-time Processing Hardware, MORRPH , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[36]  Viktor K. Prasanna,et al.  Seeking Solutions in Configurable Computing , 1997, Computer.

[37]  Dorothy E. Setliff,et al.  Towards an automatic synthesis system for real-time software , 1991, [1991] Proceedings Twelfth Real-Time Systems Symposium.

[38]  Giovanni De Micheli,et al.  Constrained software generation for hardware-software systems , 1994, Third International Workshop on Hardware/Software Codesign.

[39]  S. Trimberger,et al.  A reprogrammable gate array and applications , 1993 .

[40]  Stephen A. Edwards,et al.  Design of embedded systems: formal models, validation, and synthesis , 1997, Proc. IEEE.

[41]  Bharat P. Dave.  CRUSADE: hardware/software co-synthesis of dynamically reconfigurable heterogeneous real-time distributed embedded systems , 1999 .

[42]  Donatella Sciuto,et al.  The role of VHDL within the TOSCA hardware/software codesign framework , 1994, EURO-DAC '94.

[43]  W Powell Richard,et al.  The Road From the NASA Access-to-Space Study to a Reusable Launch Vehicle , 1998 .

[44]  R. Katz,et al.  Current radiation issues for programmable elements and devices , 1998 .

[45]  Giovanni De Micheli,et al.  Hardware-software Co-synthesis for Digital Systems , 2001 .

[46]  Richard W. Conners,et al.  MORRPH: a modular and reprogrammable real-time processing hardware , 1995, 1995 Proceedings of the IEEE International Symposium on Industrial Electronics.

[47]  Jörg Henkel,et al.  Fast timing analysis for hardware-software co-synthesis , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[48]  Ihn Kim,et al.  A fully pipelined, 700 MBytes/s DES encryption core , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[49]  Edward A. Lee,et al.  A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem , 1994, CODES.

[50]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[51]  R. W. Taylor,et al.  A self-reconfiguring processor , 1993 .