The European Logarithmic Microprocessor

In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realized? Here, we describe the European Logarithmic Microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful, and that for 32-bit work, logarithmic arithmetic may now be the technique of choice.

[1]  J. Kadlec,et al.  Performance of the European logarithmic microprocessor , 2003, SPIE Optics + Photonics.

[2]  Mark G. Arnold.  A VLIW architecture for logarithmic arithmetic , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[3]  David Lewis,et al.  A 30-b integrated logarithmic number system processor , 1991 .

[4]  Thanos Stouraitis,et al.  A very-long instruction word digital signal processor based on the logarithmic number system , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[5]  Jirí Kadlec,et al.  Arithmetic on the European Logarithmic Microprocessor , 2000, IEEE Trans. Computers.

[6]  David M. Lewis.  An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System , 1990, IEEE Trans. Computers.

[7]  Fred J. Taylor,et al.  A 20 Bit Logarithmic Number System Processor , 1988, IEEE Trans. Computers.

[8]  Mark G. Arnold,et al.  Unrestricted faithful rounding is good enough for some LNS applications , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[9]  Rui-Lin Chen,et al.  Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost , 2000, IEEE Trans. Computers.

[10]  David Lewis.  114 MFLOPS logarithmic number system arithmetic unit for DSP applications , 1995 .

[11]  J. Kadlec,et al.  The European Logarithmic Microprocessor - a QR RLS application , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[12]  John N. Coleman,et al.  A 32 bit logarithmic arithmetic unit and its performance compared to floating-point , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[13]  David M. Lewis.  Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit , 1994, IEEE Trans. Computers.