새로운 제어신호 생성회로를 이용한 FFT의 효율적인 구현

In This paper, we propose new control signal generator algorithm FFT twiddle factor address. The FFT's ROM is reduced 4 times by using proposed algorithm. In the case of the ROM, it is shown that by the proposed method, 256 point radix-2⁴ FFT, the area and power consumption can be reduced 30%, 8% respectively, 1024 point radix-2⁴ FFT, the area and power consumption can be reduced 58%, 37%, respective with conventional method.