Verification and Scheme Implementation of Parallel Automata

Abstract The parallel automaton is considered which is the functional model of a discrete control device which allows taking into account the parallel character of logical control devices. The verification of parallel automata lies in testing all transitions in the graph of the complete states of automata and is conducted based on simulation. The software tools for constructing the compact tests for verifying the parallel automaton and for obtaining the VHDL model of parallel automata aimed at implementing their scheme are proposed. The obtained algorithmic VHDL models of the automata are synthesizable, which allows obtaining the scheme implementations of parallel automata in various design libraries.