Continuous-Time Delta-Sigma Converters with Finite-Impulse-Response (FIR) Feedback

Clock jitter is a fundamental problem in continuous-time Δ Σ modulators. While many approaches have been proposed to deal with this problem, finite-impulse-response (FIR) feedback is perhaps the most effective. It turns out that FIR feedback has other benefits—it improves the modulator’s linearity for a given power dissipation, reduces the effect of the quantizer’s data-dependent jitter, and enables the use of chopping “for free.” It is an architectural technique that combines the benefits of single-bit and multi-bit operation, and has proven itself to be robust and scalable, applicable to Δ Σ data converters targeting a variety of specifications, and across process nodes. This work reviews the key challenges encountered in the design of high performance delta-sigma data converters, and describes the role of FIR feedback in addressing these challenges. The prospect of using FIR feedback to achieve wide bandwidths is examined, and promising directions are reviewed.

[1]  Robert Weigel,et al.  A 0.039 mm$^2$ Inverter-Based 1.82 mW 68.6$~$ dB-SNDR 10 MHz-BW CT-$\Sigma\Delta$ -ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques , 2014, IEEE Journal of Solid-State Circuits.

[2]  Shanthi Pavan.  Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters , 2018, 2018 IEEE Custom Integrated Circuits Conference (CICC).

[3]  Gabor C. Temes,et al.  Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization , 1996, Proc. IEEE.

[4]  Shanthi Pavan,et al.  Alias Rejection of Continuous-Time $\Delta\Sigma$ Modulators With Switched-Capacitor Feedback DACs , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Shanthi Pavan,et al.  A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback , 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

[6]  O. Oliaei,et al.  Sigma-delta modulator with spectrally shaped feedback , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[7]  Shanthi Pavan,et al.  A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth , 2019, 2019 Symposium on VLSI Circuits.

[8]  Amrith Sukumaran,et al.  Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback , 2014, IEEE Journal of Solid-State Circuits.

[9]  Shanthi Pavan,et al.  Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Shanthi Pavan,et al.  Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[11]  Patrick Satarzadeh,et al.  A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[12]  Andrew Adams,et al.  A 10/20/30/40 MHz Feedforward FIR DAC Continuous-Time $\Delta\Sigma$ ADC With Robust Blocker Performance for Radio Receivers , 2016, IEEE Journal of Solid-State Circuits.

[13]  Hae-Seung Lee,et al.  15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[14]  Shanthi Pavan.  Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Trond Ytterdal,et al.  A 1 MHz BW 34.2 fJ/step Continuous Time Delta Sigma Modulator With an Integrated Mixer for Cardiac Ultrasound , 2017, IEEE Transactions on Biomedical Circuits and Systems.

[16]  Sunsik Woo,et al.  A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Shanthi Pavan.  Systematic Design Centering of Continuous Time Oversampling Converters , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Stacy Ho,et al.  A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[19]  Sujith Billa,et al.  Analysis and Design of Continuous-Time Delta–Sigma Converters Incorporating Chopping , 2017, IEEE Journal of Solid-State Circuits.

[20]  B. M. Putter,et al.  /spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[21]  Maurits Ortmanns,et al.  A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Sujith Billa,et al.  15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[23]  Bruce A. Wooley,et al.  A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter , 1993 .

[24]  Gabor C. Temes,et al.  A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Shanthi Pavan,et al.  Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  Hae-Seung Lee,et al.  A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS , 2015, IEEE Journal of Solid-State Circuits.

[27]  Shanthi Pavan,et al.  Design Techniques for Wideband Single-Bit Continuous-Time $\Delta\Sigma$ Modulators With FIR Feedback DACs , 2012, IEEE Journal of Solid-State Circuits.

[28]  José B. Silva,et al.  A 2.8 mW ΔΣ ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[29]  Stacy Ho,et al.  Signal processing and analog/RF circuit design: cross-discipline interactions and technical challenges , 2016, APSIPA Transactions on Signal and Information Processing.

[30]  W. Snelgrove,et al.  Clock jitter and quantizer metastability in continuous-time delta-sigma modulators , 1999 .

[31]  Shanthi Pavan,et al.  Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.